Attempts to increase device integration density in microelectronic integrated circuits have typically resulted in the fabrication of smaller and smaller devices that are spaced more closely together. In order to electrically access these devices, conventional techniques to photolithographically define the location of contact holes to these devices have also had to improve. Such improvements have typically included the development of photolithographic alignment techniques having reduced tolerances. Alternatively, attempts to reduce contact hole size may not represent an acceptable approach when forming highly integrated devices because reductions in contact hole size typically lead to substantial and unacceptable increases in contact resistance.
Techniques to reduce photolithographic alignment tolerances have typically not scaled at the same rate as techniques to scale the size of microelectronic devices. To address this limitation associated with photolithographic alignment, self-aligned contact hole fabrication techniques that are less dependent on photolithographic accuracy have been developed.
A method of forming self-aligned contact holes is taught in U.S. Pat. No. 5,897,372 to Howard entitled “Formation of a self-aligned integrated circuit structure using silicon-rich nitride as a protective layer”. According to the U.S. Pat. No. 5,897,372, a gate electrode surrounded by an upper protection layer and a side-wall spacer is formed on a semiconductor substrate. A thin silicon-rich silicon nitride layer and a thick inter-layer insulating layer are sequentially formed on the entire surface of the resultant structure. The inter-layer insulating layer and the silicon-rich silicon nitride layer are dry-etched in sequence to form a self-aligned contact hole exposing the substrate between the gate electrodes. Here, a width of the self-aligned contact hole is wider than a space between the gate electrodes in order to maximize the exposed area of the substrate. Accordingly, an edge portion of the protection layer on the gate electrode is exposed by the self-aligned contact hole. At this time, in the event both the protection layer and the spacer are formed of a silicon oxide layer, the gate electrode may be exposed due to the over etching during a dry-etching process for forming the self-aligned contact hole. Thus, in order to overcome the above problem, both the protection layer and the spacer should be formed of silicon nitride layer having etch selectivity with respect to the inter-layer insulating layer or the thickness of the silicon-rich silicon nitride layer should be increased. However, the silicon nitride layer and the silicon-rich silicon nitride layer have higher dielectric constants than the silicon oxide layer. Therefore, the parasitic capacitance between the interconnection filling the self-aligned contact hole and the gate electrode is increased and such increase may degrade the electrical characteristics of the integrated circuit.
As a result, such self-aligned contact hole fabrication techniques may still be prone to reliability problems when photolithographic alignment techniques having relatively large alignment tolerances are used. Thus, notwithstanding such self-alignment techniques, there continues to be a need for improved methods of forming contact holes in highly integrated circuit substrates.